170517 - Layout-Oriented Defect Set Reduction for Fast Circuit Simulation

170524 - Detailed Routing Violation Prediction During Placement Using Machine Learning

170718 - Power-Supply-Variation-Aware Timing Analysis of Synchronous Systems

170816 - embedded deterministic test points

170823 - Prognosis of NBTI Aging Using a Machine Learning Scheme

171012 - Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks

171214 - Analysis_of_Resistive_Bridge_defect_Delay_Behavior_in_the_Presence_of_Process_Variation

171228 - Very Deep Convolutional Networks for Large-Scale Image Recognition

180201 - Scan-Chain Intra-Cell Aware Testing

180208 - Rethinking the Convolutional Neural Network Architectures for Computer Vision Application

180315 - On-Chip Lifetime Prediction for Dependable Many-Processor SoCs based on Slack-Delay and IDDX Data Fusion

180412 - On_Detecting_Bridges_Causing_Timing_Failures

180726 - DFM-Aware_Fault_Model_and_ATPG_for_Intra-Cell_and_Inter-Cell_Defects

180830 - Multi-Label-Active-Learning-with-Label-Correlation-for-Image-Classification

20170106__粘育騰__Defect-Oriented_Cell-Internal_Testing

20170517__粘育騰__Layout-Oriented_Defect_Set_Reduction_for_Fast_Circuit_Simulation

20170921__粘育騰__Cell-Aware_Analysis_for_Small-Delay_Effects_and_Production_Test_Results_from_Different_Fault_Models

20180118__粘育騰__Silicon_Evaluation_of_Cell-Aware_ATPG_Tests_and_Small_Delay_Tests

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20180503__李東振__Bridge_Over_Troubled_Wafers_Critical_Area_Based_Pattern_Generation

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20180802__李東振__Putting_Wasted_Clock_Cycles_to_Use_Enhancing_Fortuitous_Cell-Aware_Fault_Detection_with_Scan_Shift_Capture

20180823__粘育騰__Cell_Aware_and_Stuck-Open_Tests

20180920__胡鈺邦__A_Bridging_Fault_Model_for_Line_Coverage_in_the_Presence_of_Undetected_Transition_Faults

20180927__李東振__Small_Delay_Fault_Model_for_Intra-Gate_Resistive_Open_Defects

20181004__潘宇晨__An_Overview_of_Gradient_Descent_Optimization_Algorithms

20181018__張碩文__Challenges_in_Cell-Aware_Test

20181025__洪維澤__A_Machine_Learning_Framework_to_Identify_Detailed_Routing_Short_Violations_from_a_Placed_Netlist

20181101__粘育騰__Exploiting_Path_Delay_Test_Generation

20181115__黃俊揚__Accurate_Prediction_of_Detailed_Routing_Congestion

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20181213__潘宇晨__Learning-Based_Prediction_of_Embedded_Memory_Timing_Failures_During_Initial_Floorplan_Design

20181220__張碩文__Total_Critical_Area_Based_Testing

20181227__洪維澤__RouteNet_Routability_Prediction_for_Mixed-Size_Designs_Using_Convolutional_Neural_Network

20190103__粘育騰__Fast_and_Waveform-Accurate_Hazard-Aware_SAT-Based_TSOF_ATPG

20190213__李東振__Cell-Aware_Diagnosis_Defective_Inmates_Exposed_in_their_Cells

20190221__張碩文__DPPM_Reduction_Methods and_New_Defect_Oriented_Test_Methods_Applied

20190307__潘宇晨__Q-Learning_in_Continuous_State_and_Action_Space

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20190502__潘宇晨__Deep_Reinforcement_Learning_with_Double_Q-Learning

20190516__張碩文__Towards_Improvement_of_Mission_Mode_Failure_Diagnosis_for_System-on-Chip

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20190815__張碩文__Defect-Location_Identification_for_Cell-Aware_Test

20190822__李東振__Bridging_Defects_Resistance_Measurements_in_a_CMOS_Process

20190829__洪維澤__Routability-Driven_Macro_Placement_with_Embedded_CNN-Based_Prediction_Model

20190905__粘育騰__A_Nover_Test_Generation_Method_for_Small-Delay_Defects_with_User-Defined_Fault_model

20190919__潘宇晨__Supervised-Learning_Congestion_Predictor_For_Routability-Driven_Global_Routing

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20191024__葉季佑__Machine_Learning-Based_Pre-Routing_Timing_Prediction_with_Reduced_Pessimism

20191121__張碩文__Characterization_And_Testing_of_Digital_Library_Cells_For_Partial_Short_Defects

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20191205__李嘉運__Cell-aware_Experiences_in_a_High-Quality_Automotive_Test_Suite

20191212__李晨弘__Efficient_Cell-Aware_Defect_Characterization_for_Multi-bit_Cells

20200206__陳玥融__Early_Stag_ DRC_Prediction_Using_Ensemble_Machine_Learning_Algorithms

20200213__陳柏諺__Scalable_Variational_Gaussian_Process_Classification

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20200319__洪維澤__Design_Rule_Violation_Hotspot_Prediction_Based_on_Neural_Network_Ensembles

20200326__潘宇晨__CongestionNet_Routing_Congestion_Prediction_Using_Deep_Graph_Neural_Networks

20200409__張碩文__B-open_A_New_Defect_in_Nanometer_Technologies_due_to_SADP_Process

20200416__葉季佑__Graph_Attention_Networks

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20200521__陳柏諺__RUSBoost_A_Hybrid_Approach_to_Alleviating_Class_Imbalance

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20200611__潘宇晨__Chip_Placement_With_Deep_Reinforcement_Learning

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20200820__李晨弘__Tightening_the_Mesh_Size_of_the_Cell-Aware_ATPG_Net_for_Catching_All_Detectable_Weakest_Faults

20200827__陳柏諺__DRC_Hotspot_Prediction_at_Sub-10nm_Process_Nodes_Using_Customized_Convolutional_Network

20201023__粘育騰__Defect-Oriented_Test_Effectiveness_in_High_Volume_Manufacturing

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20201106__陳玥融__FaceNet_A_Unified_Embedding_for_Face_Recognition_and_Clustering

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20210115__李晨弘__Fault_Modeling_and_Analysis_for_Bridging_Defects_in_a_Synchronizer

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20210205__林晉寬__Using_Wafer_Map_Features_to_Better_Predict_Die-Level_Failures_in_Final_Test

20210304__林振岡__Deep_Q-learning_from_Demonstrations

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20210401__吳佩穎__Characterization_of_Library_Cells_for_Open-circuit_Defect_Exposure_A_Systematic_Methodology

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20210722__林晉寬__Statistical_Outlier_Screening_For_Latent_Defects

20210729__陳柏諺__Mastering_the_game_of_Go_without_human_knowledge

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20210818__黃子馨__Machine_Learning_Based_Detection_Method_for_Wafer_Test_Induced_Defects

20210825__陳柏諺__Monte_Carlo_Tree_Search

20210901__吳佩穎__Speeding_up_Cell-Aware_Library_Characterization_by_Preceding_Simulation_with_Structural_Analysis

20210908__葉季佑__Automatic_Routability_Predictor_Development_Using_Neural_Architecture_Search

20210915__李嘉運__TranGen A SAT-Based ATPG for Path-Oriented Transition Faults

20210922__李晨弘__Detectability_of_Internal_Bridging_Faults_in_Scan_Chains

20210929__粘育騰__Timing-Aware_ATPG_for_High_Quality_At-speed_Testing_of_Small_Delay_Defects

20211013__陳柏諺__Spatial_Pyramid_Pooling_in_Deep_Convolutional_networks_for_visual_recognition

20211027__林晉寬__Multidimensional_Parametric_Test_Set_Optimization_of_Wafer_Probe_Data_for_Predicting_in_Field_Failures_and_Setting_Tighter_Test_Limits

20211110__林振岡__Machine_Learning_Framework_for_Early_Routability_Prediction_with_Artificial_Netlist_Generator

20211117__黃子馨__GCN-RL_Circuit_Designer_Transferable_Transistor_Sizing_with_Graph_Neural_Networks_and_Reinforcement_Learning

20211124__吳佩穎__Cell-aware_test_generation_time_reduction_by_using_switch-level_ATPG

20211201__黃子馨__GCN-RL_Circuit_Designer_Transferable_Transistor_Sizing_with_Graph_Neural_Networks_and_Reinforcement_Learning

20211208__李嘉運__Two Dimensional Space of Close to Functional Path Delay Faults for Test Generation

20211208__粘育騰__Accurate_Estimation_of_Test_Pattern_Counts_for_a_Wide-Range_of_EDT_InputOutput_Channel_Configurations

20211215__陳亮廷__A_Reinforcement_Learning-Based_Framework_for_Solving_Physical_Design_Routing_Problem_in_the_Absence_of_Large_Test_Set

20220105__楊尊堯__Gate-Exhaustive_and_Cell-Aware_pattern_sets_for_industrial_designs

20220119__王詠正__LAIDAR_Learning_for_Accuracy_and_Ideal_Diagnostic_Resolution

20220126__蔡丞翔__Detection of Internal Stuck-open Faults in Scan Chains

20220216__粘育騰__A_Learning-Based_Methodology_for_Accelerating_Cell-Aware_Model_Generation

20220221__林晉寬__An_Improved_AdaBoost_Tree-Based_Method_for_Defcctive_Products_Identification_in_Wafer_Test

20220302__林振岡__Lookahead_Placement_Optimization_with_Cell_Library-based_Pin_Accessibility_Prediction_via_Active_Learning

20220309__黃子馨__AutoCkt_Deep_Reinforcement_Learning_of_Analog_Circuit_Designs

20220323__吳佩穎__Multi-Transition_Fault_Model_(MTFM)_ATPG_patterns_towards_achieving_0_DPPB_on_automotive_design

20220413__王詠正__Wafer_Defect_Pattern_Labeling_and_Recognition_Using_Semi_Supervised_Learning

20220420__蔡丞翔__On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation

20220427__粘育騰__Improving_the_Detectability_of_Resistive_Open_Faults_in_Scan_Cells

20220518__林晉寬__Machine_Learning-Based_Overkill_Reduction_through_Inter-Test_Correlation

20220601__林振岡__Detailed_Routing_Short_Violation_Prediction_Using_Graph-Based_Deep_Learning_Model

20220608__黃子馨__Trust_Region_Method_with_Deep_Reinforcement_Learning_in_Analog_Design_Space_Exploration

20220615__吳佩穎__Testing_the_hold_time_fault_for_large_industrial_design

20220622__陳亮廷__Circuit_Routing_Using_Monte_Carlo_Tree_Search_and_Deep_Reinforcement_Learning

20220629__王詠正__Efficient_Cell_Aware_Defect_Characterization_for_Multi_bit_Cells

20220706__蔡丞翔__Scan-Chain Intra-Cell Aware Testing

20220720__林晉寬__A_Deep_Larning-Based_Screning_Method_for_Improving_the_Quality_and_Reliability_of_Integrated_Passive_Devices

20220727__林振岡__A_Deep_Transfer_Learning_Design_Rule_Checker_with_Synthetic_Training

20220810__黃子馨__Graph_Classification_Tradeoffs_between_Deep_Neural_Network_Architecture_and_Graph_Topology

20220824__吳佩穎__Robust_Test_Pattern_Generation_for_Hold-time_Faults_in_Nanometer_Technologies

20220907__陳亮廷__GeniusRoute_A_New_Analog_Routing_Paradigm_Using_Generative_Neural_Network_Guidance

20220914__王詠正__Test_generation_for_open_and_delay_faults_in_CMOS_circuits

20220921__蔡丞翔__On_Improving_Transition_Test_Set_Quality_to_Detect_CMOS_Transistor_Stuck-Open_Faults

20221005__林振岡__PROS_A_Plug-in_for_Routability_Optimization_applied_in_the_State-of-the-art_commercial_EDA_tool_using_deep_learning

20221012__黃子馨__High_Dimensional_Bayesian_Optimization_for_Analog_Integrated_Circuit_Sizing_Based_on_Dropout_and_gm_ID_Methodology

20221026__陳亮廷__REST_Constructing_Rectilinear_Steiner_Minimum_Tree_via_Reinforcement_Learning

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20221130__王詠正__A_Comprehensive_Learning_Based_Flow_for_Cell_Aware_Model_Generation

20221207__蔡孟霖__Local_Bayesian_Optimization_For_Analog_Circuit_Sizing

20221214__陳亭維__Chaff Engineering an Efficient SAT Solver

20221221__蘇正__Efficient_Cell-Aware_Fault_Modeling_by_Switch-Level_Test_Generation

20230111__郭紘如__High-Correlation_3D_Routability_Estimation_for_Congestion-guided_Global_Routing

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20230222__王詠正__A_Novel_BIST_Algorithm_for_Low-Voltage_SRAM

20230322__蔡丞翔__Test_Generation_for_Timing-Crtical_Transition_Faults

20230328__林晉寬__VTS2023_rehearsal

20230419__蔡孟霖__Domain_Knowledge-Based_Auomated_Analog_Circuit_Design_with_Deep_Reinforcement_Learning

20230503__陳亭維__IMPROVING SAT SOLVER HEURISTICS WITH GRAPH

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20230517__郭紘如__GoodFloorplan_Graph_Convolutional_Network_and_Reinforcement_Learning-Based_Floorplanning

20230524__林晉寬__口試投影片

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20230614__許賀捷__Fault Modeling and Detection for Drowsy SRAM Caches

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20230628__王詠正__Defect_Oriented_Fault_Analysis_for_SRAM

20230710__粘育騰__Defect-Based_Test_Methodologies

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20230816__郭紘如__RL-Ripper_ A_Framework_for_Global_Routing_Using_Reinforcement_Learning_and_Smart_Net_Ripping_Techniques

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20231024__蔡孟霖__Generalizable_Floorplanner_through_Corner_Block_List_Representation_and_Hypergraph_Embedding

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20231121__蘇正__Predicting_IC_Defect_Level_using_Diagnosis

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20231206__鍾定宇__Global_Routing_Under_a_Congestion-Aware_Reinforcement_Learning_Model

20231212__李弦宸__Test_Pattern_Compression_&_Test_Response_Compaction

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20240116__陳泓佑__SAT-Based_ATPG_Testing_of_Inter-_and_Intra-Gate_Bridging_Faults

20240123__陳亭維__Accelerate_SAT-based_ATPG_via_Preprocessing_and_New_Conflict_Management_Heuristics

20240130__陳亮廷__rehearsal

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20240319__鍾定宇__Zero_Skew_Clock_Routing_with_Minimum_Wirelength

20240326__李弦宸__Open_defects_in_CMOS_RAM_address_decoders

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20240416__陳泓佑__Hierarchical_Reinforcement_Learning_for_Chip-macro_Placement_in_Integrated_Circuit

20240430__蔡孟霖__LAMPlace_Legalization_Aided_RL_Based_Macro_Placement

20240507__陳亭維__TEA_A_Test_Generation_Algorithm_for_Designs_with_Timing_Exceptions

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20240618__郭紘如__Fast_Timing-Model_Independent_Buffered_Clock-Tree_Synthesis

蔡孟霖

陳亭維

蘇正

郭紘如

許賀捷

鍾定宇

李弦宸

陳冠佑

陳泓佑